Charge Configuration Memory Devices: Energy Efficiency and Switching Speed

Year: 2022

Authors: Mraz A.; Venturini R.; Svetin D.; Sever V.; Mihailovic I.A.; Vaskivskyi I.; Ambrozic B.; Drazic G.; D’Antuono M.; Stornaiuolo D.; Tafuri F.; Kazazis D.; Ravnik J.; Ekinci Y.; Mihailovic D.

Autors Affiliation: Jozef Stefan Inst, Complex Matter Dept F7, Ljubljana 1000, Slovenia; Univ Ljubljana, Fac Math & Phys, Ljubljana 1000, Slovenia; CENN Nanoctr, Ljubljana 1000, Slovenia; Jozef Stefan Int Postgrad Sch, Ljubljana 1000, Slovenia; Natl Inst Chem, Dept Mat Chem, Ljubljana 1000, Slovenia; Univ Napoli Federico II, Dipartimento Fis Ettore Pancini, I-80126 Naples, Italy; Complesso Monte St Angelo, CNR SPIN, I-80126 Naples, Italy; CNR Ist Nazl Ott CNR INO, I-50125 Florence, Italy; Paul Scherrer Inst, CH-5232 Villigen, Switzerland; Univ Ljubljana, Fac Elect Engn, Ljubljana 1000, Slovenia.

Abstract: Current trends in data processing have given impetus for an intense search of new concepts of memory devices with emphasis on efficiency, speed, and scalability. A promising new approach to memory storage is based on resistance switching between charge-ordered domain states in the layered dichalcogenide 1T-TaS2. Here we investigate the energy efficiency scaling of such charge configuration memory (CCM) devices as a function of device size and data write time ?W as well as other parameters that have bearing on efficient device operation. We find that switching energy efficiency scales approximately linearly with both quantities over multiple decades, departing from linearity only when ?W approaches the 0.5 ps intrinsic switching limit. Compared to current state of the art memory devices, CCM devices are found to be much faster and significantly more energy efficient, demonstrated here with two-terminal switching using 2.2 fJ, 16 ps electrical pulses.

Journal/Review: NANO LETTERS

Volume: 22 (12)      Pages from: 4814  to: 4821

More Information: This project has received funding from the EU-H2020 research and innovation program under Grant Agreement 654360, NFFA-Europe, having benefited from the access provided by Paul Scherrer Institute in Villigen, Switzerland within the framework of the NFFA-Europe Transnational Access Activity. We acknowledge the help of L. Cindro from F9 at JSI on contact bonding. We thank the support from the Slovenian Research Agency (Grant P1-0040; Grant PR-08972 to A.M., Grant PR-10496 to R.V., Grant PR-06158 to A.K., Grant PR-07589 to J.R., Grant I0-0005 to D.S., Grant J2-3041 to G.D.), Slovene Ministry of Education, Science and Sport (Grant C3330-19-952005, Raziskovalci-2.1-IJS-952005), ERC AdG (Grant GA320602, TRAJECTORY), and ERC PoC (Grant GA767176, Umem4QC). We thank the CENN Nanocenter for the use of AFM, FIB, and DaLI. This project has received funding from the European Union´s Horizon 2020 research and innovation program under the Marie Sklodowska-Curie Grant Agreement No 701647, PSI-FELLOW-II-3i. F.T. has been supported by the Project SQUAD-Programma STAR PLUS 2020.
KeyWords: charge configuration memory; TaS2; ultrafast; energy-efficient; cryogenic; nonvolatile

DOI: 10.1021/acs.nanolett.2c01116

Citations: 8
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